Scanning Tunneling Microscope (STM) is a high-resolution surface analysis instrument based on the quantum tunneling effect, capable of atomic-level surface topography imaging and atomic-level surface manipulation. With an ultra-high lateral resolution of 0.01 nm and an ultra-high vertical resolution of 0.001 nm, it is widely applied in cutting-edge research fields such as materials science, surface physics, nanoscience, catalytic chemistry, and life science, serving as the core equipment for characterization and manipulation at the nanoscale. The high-voltage scanning drive power supply is a critical core component of the STM, providing high-precision, high-linearity and ultra-low-drift high-voltage drive signals for piezoelectric ceramic scanner tubes to control their nano-scale precise movement along the X, Y and Z axes and realize surface scanning imaging and topography characterization of samples. Its output linearity, long-term drift characteristics, low-noise performance and resolution directly determine the imaging resolution, image stability and topography measurement accuracy of the STM. STMs impose extremely stringent performance requirements on high-voltage scanning drive power supplies. The X/Y axis scanning drive generally requires bipolar high-voltage output of ±200 V ~ ±300 V, while the Z-axis feedback drive requires unipolar high-voltage output of 0 ~ 300 V. The specifications demand non-linear error ≤ ±0.01%, 8-hour continuous operating voltage drift ≤ ±0.005%, peak-to-peak output ripple ≤ 100 μV, and voltage adjustment resolution ≤ 1 mV. Failure to meet these criteria will cause non-linear distortion, drift and increased noise in scanned images, disable atomic-level high-resolution imaging, and even undermine stable tunneling current feedback. Traditional high-voltage scanning drive power supplies adopt topologies such as direct high-voltage op-amp driving and transformer boosting, suffering from poor output linearity, severe temperature drift, insufficient long-term stability and high output noise, which cannot satisfy the atomic-level precision driving requirements of STMs. Relevant designs must strictly comply with standards including GB/T 32840-2016 *General Specification for Scanning Tunneling Microscopes*, GB/T 27760-2011 *Scanning Probe Microscopes — Terminology*, and JJF 1408-2013 *Calibration Specification for Scanning Tunneling Microscopes*, while meeting the core demands of STMs for high linearity, ultra-low drift and low noise. Targeting the key application requirements and technical challenges of STM high-voltage scanning drive power supplies, this methodology establishes a full-process general technical framework covering high-linearity topology design, ultra-low drift suppression, full-link low-noise optimization, closed-loop feedback control and long-term stability design. It accommodates the high-voltage scanning drive needs of various scanning probe microscopes such as STMs, atomic force microscopes (AFMs) and near-field optical microscopes, providing standardized design criteria for performance improvement and domestic substitution of Chinese scanning probe microscopes. Addressing the core design challenges of high linearity, ultra-low drift and low noise in STM applications, this methodology adopts the main architecture of **low-voltage precision linear amplification + high-voltage floating rail power amplification + full-digital adaptive temperature compensation**, combined with full-range linearity calibration and ultra-low-noise optimization. It fundamentally overcomes the technical bottlenecks of traditional high-voltage drive power supplies regarding poor linearity, large drift and high noise, achieving non-linear error within ±0.01%, 8-hour voltage drift within ±0.005% and ultra-low output ripple below 100 μV, which fully meets the atomic-level precision driving requirements of STMs. The design follows five core criteria: First, a composite amplification topology of **low-voltage precision linear amplification + high-voltage floating rail power amplification** is adopted as the core for high-linearity, low-noise and wide-bandwidth high-voltage driving. This topology separates precise signal amplification from high-voltage power amplification: the low-voltage stage realizes precise linear amplification and closed-loop control of input signals, while the high-voltage stage performs power amplification and high-voltage output. It ensures excellent linearity and low noise while delivering high-voltage high-current driving capability, perfectly matching the capacitive load characteristics of piezoelectric ceramic scanner tubes. The low-voltage precision linear amplification unit adopts a differential amplifier circuit composed of low-noise, low-drift and high-gain precision operational amplifiers to achieve precise linear amplification of input control signals. An input low-voltage analog signal of ±10 V corresponds to a high-voltage output of ±300 V; the amplification factor is precisely configured via high-precision low-drift resistors, and closed-loop feedback guarantees a linear relationship between input and output. JFET-input precision op-amps with input offset voltage ≤ 10 μV, offset voltage drift ≤ 0.1 μV/°C and input noise density ≤ 5 nV/√Hz @1 kHz are selected to ensure ultra-low drift, low noise and high linearity at the source. The high-voltage floating rail power amplification unit adopts a push-pull power amplifier circuit with complementary high-voltage power transistors. Its power supply uses a floating rail design that dynamically adjusts with the output voltage, maintaining a constant voltage drop of approximately 20 V across the power transistors. This keeps the transistors operating in the linear region while significantly reducing power consumption and heat generation, eliminating temperature drift and linearity degradation caused by excessive heating in conventional fixed-rail high-voltage amplifiers and improving overall efficiency and long-term stability. High-voltage MOSFETs with high withstand voltage (≥500 V), high linearity and low junction capacitance are used to ensure linear operation across the full ±300 V output range with excellent wide-band response and ripple-free driving of capacitive loads without overshoot or oscillation. The high-voltage feedback sampling unit uses a differential voltage divider network with high-precision low-drift resistors to scale down high-voltage output for closed-loop negative feedback, securing highly linear input-output correlation. High-precision metal foil resistors with temperature coefficient ≤ 2 ppm/°C and tolerance ±0.005% are strictly matched and aged to guarantee long-term stability and temperature consistency of the division ratio. Independent fully isolated amplification channels are configured for the X, Y and Z axes to eliminate inter-channel crosstalk and ensure synchronous and independent triaxial driving. Second, full-range linearity optimization adopts a three-tier guarantee scheme: **precision hardware matching + software full-range multi-point calibration + real-time non-linear error compensation**, restricting non-linear error within ±0.01% across the entire output range. At the hardware level, gain-setting resistors and feedback divider resistors are selected from matched batches of high-precision metal foil resistors with ratio matching error ≤ ±0.002% and subjected to high-low temperature cycling aging to eliminate internal stress and ensure stable resistance ratios. Precision op-amps with high open-loop gain (≥120 dB) and high common-mode rejection ratio (≥100 dB) minimize gain-related linearity variations, limiting inherent hardware non-linearity within ±0.02%. At the software calibration stage, an FPGA-based fully digital control system performs no fewer than 50 evenly spaced calibration points across the full -300 V ~ +300 V output range. A 6.5-digit high-precision multimeter records actual output values, and a high-order polynomial non-linear correction model is established and stored in the FPGA. During operation, the FPGA dynamically corrects the control signal in real time according to the pre-stored model, suppressing overall non-linear error to within ±0.01% and preventing image distortion. Triaxial synchronous calibration ensures consistent linearity across X/Y/Z axes to enhance imaging quality. Third, ultra-low drift suppression implements a four-tier drift reduction strategy: **ultra-low-drift component selection + hardware temperature compensation + full-temperature-range adaptive software compensation + optimized thermal design**, achieving 8-hour continuous operating voltage drift ≤ ±0.005%. Key components adopt ultra-low-temperature-coefficient models: low-drift Zener voltage references with temperature coefficient ≤ 0.5 ppm/°C and long-term stability ≤ 2 ppm/1000 h; precision op-amps with offset drift ≤ 0.1 μV/°C; metal foil resistors with TC ≤ 2 ppm/°C; and NP0 ceramic capacitors with TC ≤ ±30 ppm/°C to minimize inherent thermal drift. Analog temperature compensation networks with positive/negative TC resistors cancel temperature-induced parameter variations in amplifiers and resistors, stabilizing gain and offset across temperatures. Multiple high-precision platinum resistance temperature sensors monitor critical component temperatures during factory calibration, establishing a full-temperature-range drift polynomial model covering -10 °C ~ +50 °C. The FPGA dynamically adjusts offset and gain parameters in real time during operation to compensate thermal drift, limiting the overall temperature coefficient ≤ 0.5 ppm/°C. A fully sealed constant-temperature shielding structure maintains sensitive components such as voltage references, op-amps and divider networks at 25 °C ± 0.1 °C via local thermostats, while a full conduction cooling architecture ensures uniform temperature distribution across high-voltage power stages to eliminate thermal gradients and long-term drift. Fourth, full-link low-noise optimization adopts a three-tier noise suppression scheme: **source noise reduction + full-link multi-stage filtering + optimized shielding and grounding**, achieving peak-to-peak output ripple ≤ 100 μV and noise density ≤ 10 nV/√Hz @1 kHz. Low-noise op-amps and voltage references reduce inherent noise; low-junction-capacitance high-voltage MOSFETs minimize switching noise and high-frequency oscillation; all power amplifiers operate in pure Class A linear mode to eliminate crossover distortion; multi-stage low-noise linear regulators supply clean power with ripple below 10 μV. A seven-stage full-bandwidth filtering architecture eliminates noise across the entire signal path: RC low-pass filtering for input control signals; π-type filtering for voltage references; multi-stage LC filtering for power rails of low-voltage amplifiers; RC filtering at amplifier outputs; active filtering for floating power supplies; two-stage RC filtering at high-voltage outputs; and on-chip RC decoupling near piezoelectric loads to suppress high-frequency noise from long cables while preserving driving bandwidth for fast scanning. A dual-layer sealed shielding enclosure (inner permalloy for low-frequency magnetic shielding, outer aluminum alloy for high-frequency electric shielding) provides shielding effectiveness ≥ 120 dB. Low-voltage analog, high-voltage power and power supply circuits are isolated in independent metal cavities; sensitive analog components are enclosed in dedicated permalloy shielding boxes to block external electromagnetic interference. A single-point star grounding structure eliminates ground loops by connecting analog ground, digital ground, power ground and shielding ground to a unique main reference point, strictly separating high-current return paths from weak signal paths to prevent interference. Fifth, high-bandwidth closed-loop control and triaxial synchronous driving optimize dynamic response for fast scanning and real-time tunneling feedback. The closed-loop bandwidth exceeds 10 kHz to support high-speed scanning and instantaneous Z-axis tunneling current regulation. An FPGA-based triaxial synchronous control system generates perfectly synchronized X/Y/Z drive signals with timing accuracy ≤ 1 μV, enabling raster scanning, vector scanning, spiral scanning and other imaging modes while processing tunneling current feedback to maintain stable gap control. Automatic zero-offset calibration corrects output offset errors, and overvoltage limit protection prevents scanner tube damage and tip crashes caused by over-range driving. High-reliability protection and STM system integration serve as core supporting measures for long-term continuous operation. Every drive channel features comprehensive dual hardware/software protection including overvoltage, overcurrent, short-circuit, overtemperature and ESD protection with hardware response ≤ 1 μs to instantly cut high voltage during faults and protect expensive scanners, probes and samples. Soft-start functionality eliminates power-on overshoot, while dedicated tip crash protection interfaces link with tunneling current detection systems to rapidly retract the Z-axis upon abrupt current surges. Modular configurations support customizable voltage ranges (±100 V ~ ±500 V), channel counts and bandwidths for ultra-high-vacuum low-temperature STMs, atmospheric STMs and portable compact systems with tailored low-temperature stability, anti-interference and low-power designs. Standard analog (±10 V) and digital interfaces (RS232, USB, Ethernet, synchronous triggering) enable seamless integration with STM scanning control, tunneling detection and data acquisition systems for full-link synchronized imaging. The design complies with GB/T 17626 Class B EMC standards to avoid interference with weak tunneling current measurements. All critical components adopt high-reliability industrial-grade selection with Class I derating (voltage ≤70%, current ≤60%, temperature ≤80% of ratings); rigorous environmental cycling, aging and vibration testing verify an MTBF ≥ 50,000 hours for long-term laboratory operation. In summary, this methodology forms a complete technical framework covering high-linearity topology, ultra-low drift suppression, full-link low-noise optimization and closed-loop control, resolving the traditional drawbacks of poor linearity, large drift and high noise in high-voltage STM drive power supplies. It achieves non-linear error within ±0.01% via composite amplification and three-tier linearity guarantee, 8-hour drift within ±0.005% via four-tier drift suppression, and ultra-low ripple below 100 μV via three-tier noise reduction. Fully compliant with atomic-level precision driving requirements for STMs, it is widely applicable to all types of scanning probe microscopes, providing core technical support for performance improvement and domestic independent development of Chinese scientific instruments.