Full digital control serves as the core technical foundation of modern high‑voltage power supplies and provides critical support for high‑precision control, intelligent operation & maintenance, and flexible adaptation to multi‑scenario requirements. It eliminates the fundamental drawbacks of traditional analog control circuits, including fixed parameters, complicated debugging, poor adaptability, and inability to implement sophisticated intelligent algorithms. It is widely applicable to all high‑voltage power supply topologies such as linear power supplies, switching power supplies, pulsed power supplies, and resonant power supplies, covering the full voltage range of 1 kV~1000 kV and the full power range of 1 W~10 MW for general high‑voltage power supply products. The standardized design of the full digital control architecture and hardware platform directly determines the control accuracy, dynamic response, reliability, and scalability of high‑voltage power supplies, as well as product R&D cycles, mass production consistency, and maintenance convenience. The design of general full digital control architectures for high‑voltage power supplies faces eight core technical challenges.
First, the challenge of universal full‑scenario adaptability. High‑voltage power supplies with different topologies, voltage levels, and power ratings impose vastly different requirements on the control architecture. The control hardware platform must feature strong universality and scalability, supporting mainstream topologies such as flyback, forward, LLC, full bridge, Marx, and linear regulation without modifying core hardware. It must cover all product categories from low‑voltage low‑power laboratory power supplies to ultra‑high‑voltage high‑power industrial power supplies. Second, the challenge of real‑time performance and control precision. High‑voltage power supplies demand extremely fast control loops, especially pulsed power supplies and fast‑response power supplies, requiring a control loop update frequency ≥100 kHz and control delay ≤1 μs, while achieving output voltage accuracy at the ppm level. This places stringent requirements on hardware computing capability, sampling precision, and timing synchronization. Third, the challenge of high reliability and anti‑interference performance. Operating in harsh environments with strong electromagnetic fields, high voltage, and large current, digital control hardware must withstand severe electromagnetic interference, high‑voltage coupling surges, and transient pulses. The platform must maintain stable operation without crashes, program runaway, or control failure. Fourth, the challenge of standardization and scalability. Due to the wide variety of high‑voltage power supply products and extensive customization demands, the control platform must adopt a standardized modular design. Core control, sampling, driving, communication, and protection units shall be configured as standard modules that can be flexibly deployed to shorten R&D cycles and ensure consistent mass production. Fifth, the challenge of multi‑channel synchronous control. Multi‑output high‑voltage power supplies, Marx pulsed power supplies, and mass spectrometer high‑voltage units require multi‑channel synchronous control with timing accuracy ≤100 ns and inter‑channel crosstalk ≤0.001%. Sixth, the challenge of safety redundancy and fault tolerance. As high‑voltage equipment poses significant risks, the digital control system must incorporate comprehensive hardware redundancy for core control, sampling, and protection functions. Safe shutdown shall still be guaranteed even if individual control loops fail, preventing accidents caused by loss of high‑voltage regulation. Seventh, the challenge of communication and intelligent adaptation. Modern high‑voltage power supplies require networking and intelligent functions, supporting field buses, Ethernet, and optical fiber interfaces with standard industrial protocols to enable remote control, real‑time monitoring, and data uploading compliant with Industry 4.0 and smart factory requirements. Eighth, the challenge of long lifecycle and compatibility. High‑voltage power supplies typically feature a design life ≥10 years, requiring long‑term component availability, software compatibility, cross‑generational hardware support, and upgradability to avoid maintenance difficulties caused by product iteration.
Addressing the core challenges of full digital control architectures for general high‑voltage power supplies, this methodology establishes a universal framework of “dual‑core heterogeneous DSP+FPGA architecture + standardized modular hardware platform + fully isolated safety protection system”. It adapts to all topologies, voltage levels, and power ratings, breaking through the limitations of poor adaptability in analog control and excessive customization in conventional digital platforms. The design follows eight core principles. First, a standardized dual‑core heterogeneous control architecture adopts DSP+FPGA to separate complex algorithm execution from high‑speed logic processing. The DSP handles advanced control algorithms, communication protocols, condition monitoring, and health management, while the FPGA implements PWM generation, high‑speed sampling, synchronous timing, and hardware‑level protection. Standardized pin definitions and bus structures allow flexible upgrading of computing power without hardware redesign, covering low‑power portable units to MW‑class industrial systems. Second, a fully isolated layered modular hardware platform adopts a backbone main control board plus functional extension boards. The main control board integrates DSP, FPGA, power management, reference sources, and core communication, while extension modules for high‑voltage sampling, driving, analog I/O, communication expansion, and protection support plug‑and‑play configuration. Full isolation between control and power circuits achieves ≥5 kVAC withstand voltage, with magnetic and optoelectronic isolation separating analog and digital domains to block high‑voltage interference paths. Third, a high‑precision high‑speed sampling system adopts fully differential synchronous sampling with 16‑bit to 24‑bit Σ‑Δ ADCs at up to 10 MSPS, ensuring voltage and current sampling accuracy ≤±0.01%. Independent low‑temperature‑drift reference sources with a temperature coefficient ≤±0.5 ppm/℃ guarantee long‑term stability, while fully shielded differential circuits suppress common‑mode interference in strong electromagnetic environments. Fourth, a nanosecond hardware‑based safety protection system implements all critical protection logic inside the FPGA, including overvoltage, overcurrent, short circuit, overtemperature, arcing, and insulation breakdown detection, with response time ≤1 μs and highest priority that cannot be bypassed by software. Dual redundant hardware and software protection ensure absolute safety even if the DSP crashes or malfunctions. Fifth, high‑precision multi‑channel synchronous control based on FPGA integrates high‑stability constant‑temperature oscillators with clock jitter ≤10 ns, supporting up to 32 independent PWM and trigger outputs with programmable delay steps ≤10 ns and overall synchronization accuracy ≤100 ns, fully satisfying synchronous control needs for multi‑output, Marx, and series‑connected high‑voltage systems. Sixth, a fully compatible standardized communication system integrates RS232, RS485, CAN, Ethernet, optical fiber, and USB interfaces, supporting protocols such as Modbus‑RTU/TCP, Profibus, Profinet, IEC 61850, and SCPI. All communication ports feature full isolation ≥2.5 kVAC, with reserved expansion for 5G, LoRa, and Wi‑Fi wireless modules. Seventh, enhanced anti‑interference and EMC design adopts 4~8 layer PCB layouts with separate analog, digital, and power ground planes to minimize high‑frequency loop areas. All high‑speed signals use impedance matching to eliminate reflections. The main control board adopts a fully sealed metal shielding enclosure with shielding effectiveness ≥60 dB. Three‑stage EMI filters suppress conducted interference at power inlets, while TVS and RC protection on all I/Os ensure ESD, EFT, and surge immunity meet Grade 4 requirements of GB/T 17626. Eighth, long‑lifecycle maintainability design selects industrial‑grade and automotive‑grade components with guaranteed availability exceeding 10 years. Software adopts layered modular architecture with clear separation of bottom drivers, core algorithms, and application protocols to support cross‑platform porting and upgrades. Comprehensive self‑diagnosis and logging functions enable real‑time fault recording, remote upgrading, and on‑site debugging to reduce maintenance costs throughout the product lifecycle.